SRAM 2Mbit Static RAM high-performance COMS static random access memory CY7C1011DV33-10ZSXI

Features■ Pin and function compatible with CY7C1010CV33■ High speed❐ tAA = 10 ns■ Low active power❐ ICC = 90 mA at 10 ns■ Low CMOS standby power❐ ISB2 = 10 mA■ 2.0 V data retention■ Automatic power down when deselected■ TTL-compatible inputs and outputs■ Easy memory expansion with CE and OE features■ Available in Pb-free 36-pin SOJ and 44-pin TSOP II packages

Functional DescriptionThe CY7C1010DV33 is a high performance CMOS Static RAMorganized as 256 K words by 8 bits. Easy memory expansion isprovided by an active LOW Chip Enable (CE), an active LOWOutput Enable (OE), and three-state drivers. Writing to thedevice is accomplished by taking Chip Enable (CE) and WriteEnable (WE) inputs LOW. Data on the eight I/O pins (I/O0through I/O7) is then written into the location specified on theaddress pins (A0 through A17).Reading from the device is accomplished by taking Chip Enable(CE) and Output Enable (OE) LOW while forcing Write Enable(WE) HIGH. Under these conditions, the contents of the memorylocation specified by the address pins will appear on the I/O pins.The eight input and output pins (I/O0 through I/O7) are placed ina high impedance state when the device is deselected (CEHIGH), the outputs are disabled (OE HIGH), or during a Writeoperation (CE LOW, and WE LOW).The CY7C1010DV33 is available in 36-pin SOJ and 44-pinTSOP II packages with center power and ground (revolutionary)pinout.For a complete list of related documentation, click here.

Packaging and transportation instructions

- According to the standard export packaging.

Customers can choose from cartons, wooden cases and wooden pallets according to their own requirements.

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